High-performance integrated circuits, particularly microprocessors commonly provide various modes of operation, e.g., high performance, low power, standby, or test modes. Microprocessors may operate in a high-performance mode when tasked with timing-critical applications. Some microprocessors incorporate pulse-triggered storage elements, e.g., pulse-triggered latches, registers, or flip-flops to improve performance when executing instructions associated with timing-critical applications. For example, pulse-triggered storage elements may be dispersed throughout instruction execution pipelines for improving data transfer speed between pipeline stages. Pulse-triggered storage elements capture and/or launch data in response to a pulse clock signal, i.e., a clock signal having a pulse width less than half of the clock period.
Conventional pulse-triggered storage elements trade-off performance for stability. That is, pulse-triggered storage elements offer improved performance in that only a single latch stage exists between the storage element input and output. Conversely, conventional master-slave storage elements comprise two latch stages through which input data passes before reaching the output. However, pulse-triggered storage elements are commonly not as stable as master-slave storage elements over a wide range of process variation and/or operating conditions.
The short sampling window associated with pulse-triggered storage elements causes pulse-triggered storage elements to be more sensitive to variations in process parameters and/or operating conditions. For example, pulse-triggered storage elements are more sensitive than master-slave storage elements to variations in process parameters such as transistor threshold voltage, channel length, and gate oxide thickness. Additionally, pulse-triggered storage elements are more sensitive to variations in operating conditions such as dynamically varied supply voltages, power supply drift, temperature changes, high radiation flux (causing soft errors) and the like.
Further, integrated circuits incorporating pulse-triggered storage elements, e.g., microprocessors may be operated in timing insensitive modes such as low power, standby, or test modes. When configured in an operating mode that is timing insensitive, pulse-triggered storage elements included in a microprocessor may not function properly. For example, in low power mode, the operating voltage may be lowered to such a value that the pulses would become either too narrow or too wide for reliable circuit operation.
As such, pulse-triggered storage elements are conventionally used in applications where performance is critical and variations in process parameters and/or operating conditions are minimal or may be maintained within acceptable limits. Otherwise, master-slave storage elements are conventionally used in applications where reliable operation is desired over a wide range of process variation and/or operating conditions.